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50MHz to 1000MHz, 75dB Logarithmic
Detector/Controller
variable-gain PA. As shown in the figure, the MAX2014
monitors the output of the PA through a directional cou-
pler. An internal integrator (Figure 2) compares the
detected signal with a reference voltage determined by
V SET . The integrator, acting like a comparator, increas-
es or decreases the voltage at OUT, according to how
closely the detected signal level matches the V SET ref-
erence. The MAX2014 adjusts the power of the PA to a
level determined by the voltage applied to SET. With R1 =
0 Ω , the controller mode slope is approximately
19mV/dB (RF = 100MHz).
V S
R4
Layout Considerations
As with any RF circuit, the layout of the MAX2014 circuit
affects the device’s performance. Use an abundant num-
ber of ground vias to minimize RF coupling. Place the
input capacitors (C1, C2) and the bypass capacitors
(C3–C6) as close to the IC as possible. Connect the
bypass capacitors to the ground plane with multiple vias.
Pin Configurations
TOP VIEW
OUT SET GND PWDN
8 7 6 5
1
V CC
MAX2014
C6
C5
EP
RFIN
C1
2
DETECTORS
INHI
20k Ω
OUT 8
SET 7
V OUT
V SET
+
1 2 3 4
V CC INHI INLO V CC
C2
3
INLO
20k Ω
GND
6
TOP VIEW
TDFN
4
V CC
MAX2014
PWDN
5
V CC
1
+
8
OUT
C4
C3
INHI
2
MAX2015
7
SET
INLO
3
6
GND
Figure 2. Controller-Mode Typical Application Circuit
V CC
4
5
PWDN
POWER AMPLIFIER
TRANSMITTER
GAIN-CONTROL INPUT
COUPLER
μMAX
SET-POINT
OUT
SET
LOGARITHMIC
DETECTOR
IN
DAC
20k Ω
20k Ω
MAX2014
Figure 3. System Diagram for Automatic Gain-Control Loop
10
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